A programmable logic device (PLD), such as for example a field programmable gate array (FPGA) or a complex programmable logic device (CPLD), typically uses configuration memory to store configuration data, which determines (e.g., programs or configures) the PLD's user-defined functions. As the logic capacity and complexity of PLDs increase, the number of configuration memory cells similarly increases and modern PLDs typically employ millions of configuration memory cells.
A drawback of a conventional PLD is that all of the configuration memory cells must operate properly or the PLD typically is deemed defective as it may not be able to perform a user's desired functions. Consequently, defective configuration memory cells may result in significant yield loss for PLD manufacturers. Alternatively, a conventional approach is to provide redundant portions (e.g., including logic blocks, interconnect, configuration memory, etc.) of the PLD that would be used in place of defective portions or provide the desired output signals to the defective portions, with the output signals bypassing the defective components (e.g., as disclosed in U.S. Pat. No. 5,831,907). However, this approach may add significantly to the overhead, requires significant die area to implement, and may reduce PLD performance.
As a result, there is a need for improved techniques directed to defective configuration memory cells within a PLD.